The present invention relates generally to doping non-planar structures such as those formed during the fabrication of some integrated circuits and photovoltaic cells. More particularly, the present invention relates to a method for providing a conformal dopant distribution on a non-planar silicon structure.
A common technique used in fabrication of some semiconductor devices is to dope a silicon substrate with boron and/or phosphorus to adjust the electrical properties of the silicon. There are a variety of techniques used to dope planar structures formed on a silicon substrate including ion implantation, plasma doping and dopant diffusion. As device dimensions are reduced in order to achieve better performance and reduce the manufacturing costs, however, some doping techniques like ion implantation may not be feasible. Ion implantation damages the crystal structure of the silicon due to high energy particle bombardment. This becomes problematic especially in sub-micron dimensions where the device cannot tolerate crystal damage beyond a certain level, and using ion-implantation may result in poor contacts, increased junction leakage and increase in contact resistance. Therefore, with smaller dimension devices, doping techniques such as dopant diffusion techniques that do not compromise the structural integrity of the device may provide better results.
In a dopant diffusion technique, a thin doped layer is deposited over the structure and diffused into the underlying silicon substrate using a thermal anneal process, such as a rapid thermal processing (RTP) technique. Dopant diffusion provides conformal dopant distribution with better controllability than ion implantation. One known dopant diffusion technique that has been used to dope planar silicon structures forms a thin conformal doped silicate glass layer over the planar structure using a form of chemical vapor deposition (CVD) referred to as sub-atmospheric chemical vapor deposition (SACVD). This known SACVD dopant diffusion process combines ozone (O3) with tetraethyl orthosilicate (TEOS) and an appropriate dopant, such as triethylborate (TEB) as a boron source for a BSG film and/or triethylphosphate (TEPO) as a phosphorus for a PSG film) at sub-atmospheric pressure, for example 100-700 torr, and a temperature of between 400-500° C. The deposited doped layer, such as phosphorus silicate glass (PSG) or boron silicate glass (BSG), is then be exposed to an RTP step to thermally drive the dopants into the silicon.
Further scaling of semiconductor devices in modern integrated circuit fabrication techniques have motivated the adoption of non-planar structures in logic, memory and other applications where gate, source and drain are formed above the silicon substrate. FIG. 1 is a simplified perspective view of one such non-planar structure referred to as a Fin Field Effect Transistor (FINFET). As shown in FIG. 1, a FINFET 10 is formed on top of a silicon substrate 12 having a drain 14, a source 16, a gate 18 and a FIN 20. These non-planar features may be formed by depositing and patterning polysilicon over silicon substrate 12 or by etching trenches into the silicon substrate.
Despite the desire of semiconductor manufacturers and others to adopt non-planar structures in both semiconductor devices and solar cells, there are challenges associated with doping the raised patterned silicon structures such as the drain, source and channel of FINFET 10 shown in FIG. 1. The non-planar structures do not have the structural support that planar structures have, and thus their structural form may be damaged during doping, activation and etching. Also, due to the small dimensions and shape of non-planar structures, thermal budget limitations may restrict the ability of device manufacturers to anneal damage induced during the doping process. Accordingly, improved techniques and methods for uniformly doping non-planar structures are desirable.